Glossary

A list of technical terms and abbreviations used throughout this project.

Term	Definition
CM7	Cortex-M7 — The high-performance primary core of the STM32H755.
CM4	Cortex-M4 — The auxiliary core of the STM32H755.
DDS	Data Distribution Service — A middleware standard for data-centric connectivity.
HSEM	Hardware Semaphore — A hardware block used for synchronization between the CM7 and CM4 cores.
LwIP	Lightweight IP — A small open-source TCP/IP stack used for embedded systems.
micro-ROS	An implementation of ROS 2 specifically for microcontrollers.
MPU	Memory Protection Unit — Used to define memory regions and their attributes (e.g., cacheability).
RMW	ROS Middleware Interface — The layer that abstracts the underlying DDS implementation in ROS 2.
TAP	Network TAP — A virtual network interface on the host used for simulation.
XRCE-DDS	eXtremely Resource Constrained Environments DDS — The protocol used by micro-ROS to communicate with a ROS 2 agent.